The development of CompSOC has taken more than a decade. From 2001 onwards we have been working on

• the various predictable and composable networks on chip (Aethereal, aelite, daelite)
• the predictable DRAM memory controller (Predator and RUN-DMC)
• DRAM memory power estimation (DRAMPower.info)
• the predictable partitioned/composable operating system / microkernel (CompOSe, CoMiK)
• distributed real-time power management on heterogeneous resources
• comprehensive resource management framework 
• transaction-based post-silicon debug
• variability awareness in the architecture and design flow

This research has been funded in part in the following European and Dutch projects

• MESA
• NEVA
• Scalopes
• COMCAS
• TSAR
• NEST 
• Flextiles
• T-CREST
• BENEFIC
• OpenES
• DEWI
• EMC2
• RESIST